This book commemorates five decades of research by Professor Magdy F. Iskander (Life Fellow IEEE) on materials and devices for the radiation, propagation, scattering, and applications of electromagnetic waves, chiefly in the MHz-THz frequency range as well on electromagnetics education. This synopsis of electromagnetics, stemming from the life and times of just one person, is meant to inspire junior researchers and reinvigorate mid-level researchers in the electromagnetics community. The authors of this book are internationally known researchers, including 12 IEEE fellows, who highlight interesting research and new directions in theoretical, experimental, and applied electromagnetics.

New Directions in Wireless Communications Research addresses critical issues in the design and performance analysis of current and future wireless system design. Intended for use by system designers and academic researchers, the contributions are by acknowledged international leaders in their field.

System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.

The book presents high-quality papers from the Seventh International Conference on Microelectronics and Telecommunication Engineering (ICMETE 2023). It discusses the latest technological trends and advances in major research areas such as microelectronics, wireless communications, optical communication, signal processing, image processing, Big Data, cloud computing, artificial intelligence, and sensor network applications. This book includes the contributions of national/international scientists, researchers, and engineers from both academia and the industry. The contents of this book will be useful to researchers, professionals, and students alike.

This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products. The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems. The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level.

The aim of this handbook is to summarize the recent rapidly developed real-time computing technologies, from theories to applications. This handbook benefits the readers as a full and quick technical reference with a high-level historic review of technology, detailed technical descriptions and the latest practical applications. In general, the handbook is divided into three main parts (subjected to be modified): theory, design, and application covering different but not limited to the following topics:

This book presents various design theories and methodologies for silicon-based high-sensitivity broadband receivers, including millimeter-wave radiometer chips and photoelectric receivers, which are core elements in imaging systems, data centers, and telecommunication infrastructures. As a key module in application systems, the high-sensitivity broadband receiver, not only attracts the attention of engineers and researchers in the radio-frequency and optoelectronic fields, but also garners significant interest from other disciplines, including optics, communications, and security.

This book explains the application of recent advances in computational intelligence – algorithms, design methodologies, and synthesis techniques – to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems.

Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation intends to be a comprehensive guide to Fault Injection techniques used to evaluate the dependability of a digital system. The description and the critical analysis of different Fault Injection techniques and tools will be authored by key scientists in the field of system dependability and fault tolerance.

"System level testing is becoming increasingly important. It is driven by the incessant march of complexity … which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is ¿any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail . System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.

This book brings together papers presented at the 2023 International Conference on Communications, Signal Processing, and Systems, which provides a venue to disseminate the latest developments and to discuss the interactions and links between these multidisciplinary fields. Spanning topics ranging from Communications, Signal Processing, and Systems, this book is aimed at undergraduate and graduate students in Electrical Engineering, Computer Science and Mathematics, researchers and engineers from academia and industry as well as government employees (such as NSF, DOD, DOE).